Optimization of CVD dielectric process to achieve reliable ultra low-k air gaps

The capability of CVD silicon oxide has been studied to achieve a controlled air gap between copper interconnects for sub-quarter micron CMOS technologies. Several deposition parameters have been investigated and their influence on air gap morphology and electrical performances are shown in this paper. A reliable process has been obtained from these experiments. The parasitic capacitance between lines is reduced by half using SiO2 air gap material.