A 1 OO=MIPS GaAs

microprocessor’s memory address adder, thus reducing the number of required buses from five to four and making the data path small- er. Other modifications include a re- vised pipelining of the ALU unit and a revised sequencing circuit to equalize delays in all pipeline stages. We initially specify the microproces- sor as a set of concurrent processes. We later transform the text of these process-