An offset reduction technique for dynamic voltage comparators

This paper presents a technique to reduce offset voltage of a dynamic comparator. Contrary to conventional way of measuring offset, the proposed technique is based on phase measurement of comparator output. A full-digital implementation is used to measure phase without impacting offset accuracy. Simulation results show a reduction of more than ten times in the comparator offset with a small increment in power consumption. The technique can be used during normal operation requiring less than 500ns to finish calibration, so that there is not need to break the communication link associated to the comparator. The circuit has been implemented in a 130nm TSMC standard CMOS process.