In-line yield prediction methodologies using patterned wafer inspection information

Due to the advances in in-line inspection technology it is now possible to obtain an early in-line prediction of yield. This paper introduces and compares two new in-line yield prediction methodologies: (1) multilayer critical area method and (2) defect-type-size kill-ratio method. These methods are more accurate than the past and other current approaches used in the semiconductor industry. The first method uses the design layout information along with the in-line defect data, whereas the second method uses the defect and yield data to empirically derive the kill-ratios. We demonstrate our methodologies using data collected in a real wafer fabrication facility at the polysilicon gate (Poly), and the first and second interconnect (Metal 1 and Metal 2) post etch inspection layers. We compare our in-line predictions with the actual yield.