Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer (TSL) with linear variable doping (LVD) and further research on the TSL LVD with a multiple step field plate (MSFP), a breakdown voltage (BV) model is proposed and experimentally verified in this paper. With the two-dimensional Poisson equation of the silicon on insulator (SOI) device, the lateral electric field in drift region of the thin silicon layer is assumed to be constant. For the SOI device with LVD in the thin silicon layer, the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field (ENDIF), from which the reduced surface field (RESURF) condition is deduced. The drain in the centre of the device has a good self-isolation effect, but the problem of the high voltage interconnection (HVI) line will become serious. The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device. Based on this model, the TSL LVD SOI n-channel lateral double-diffused MOSFET (nLDMOS) with MSFP is realized. The experimental breakdown voltage (BV) and specific on-resistance (Ron,sp) of the TSL LVD SOI device are 694 V and 21.3 Ω-mm2 with a drift region length of 60 μm, buried oxide layer of 3 μm, and silicon layer of 0.15 μm, respectively.