Grain Boundaries in Multicrystalline Silicon. Characterization by Admittance and EBIC Measurements

A model is introduced which describes the electrical properties of a grain boundary under electron irradiation. The barrier height lowering under e-beam irradiation of selected grain boundaries is determined by admittance measurements and can be described in the framework of the model presented. Admittance and EBIC measurements at differently processed grain boundaries (annealed, solar processed) are not uniformly correlated. Calculations based on our GB model indicate that the observed, partially diverging, trends of barrier heights and EBIC contrasts may be caused by the different levels of e-beam irradiation at which admittance and EBIC are operated. A discrete trap level at Ev + 504 meV is generated at the grain boundary interface by intentional iron contamination. In this specific case, the electrical properties of the considered grain boundary are consistently described in the framework of our model by admittance and EBIC measurements.