Terminating LoadDependent WidthOptimization of Global Inductive VLSIInterconnects

Inthis paperinterconnect wvidth isoptimnizedfor tamnatched condition toreduce PowerandDelay parameters. Widthoptimization isclotne fJrtwosets ofinterconnect terminaating concditions viz.. 1)by active gate,and 2)bypassive capacitanice. Fora driver interconnect loadmodelternninated by an active gate, a tradeoff exists between short circuit and dynamic power ininiductive initerconinects, since withwider lines dynamic powverincreases, butshort circuit power oJ' thzeloadgatedecreases diue to reducedtransient delay.Whereas, fior a line termincated bya capacitor, suchtradeoff doesnot exist. Thepower consumption continues toinicrease even withredu(ced transient delay forwiderlines. Mansyofthepreviouts researches havemodeled the active gateloadatterminating end byitsinfput paircasitic gateccapacitance. This paper showsthat suchmodeling leads toinaccuracy inestimation of power, andtherefore non-optimal widthselection, especially forlarge fan-out conditions.