A Novel Compact Model for On-Chip Vertically-Coiled Spiral Inductors

A novel compact model for on-chip vertically coiled spiral inductors is presented. The vertical metal coils are modeled by a ladder network consisting of ideal inductors and resistors. The skin and proximity effects are taken into consideration. The capacitive parasitics between relevant metal layers are modeled. A method to analytically extract the model parameters is proposed. The model prediction shows excellent agreement between the data from both simulation and measurement over the frequency range of 0.1---66.1 GHz, for a vertically coiled spiral inductor manufactured in TSMC 90 nm RF CMOS technology.