Apparatus for synchronising nrz data bit

The bit synchroniser has PLL whose loop gain is not varied sensitively to bit pattern and bit rate of NRZ data, and comprises: a phase comparator comparing the NRZ signal with the output of a VCO forming a synchronised clock pulse; a gain controller limiting the phase comparison signal to restrict the density of data transitions from the comparator; a frequency comparator comparing the VCO frequency with a signal of half the frequency of an external reference clock; a second gain controller restricting the comparator output below a predetermined level; and an N-frequency divider connecting the output of the VCO to both gain controllers. The pulse information is shaped such that its pulse width is irrelevant to either the reference or VCO clock frequencies.