DRAM device having a multilayer capacitor encapsulation layer

A capacitor of the device C is encapsulated by a multilayer encapsulation layer EL comprising a blocking layer 130 (which may be TiO 2 , Ta 2 O 5 , BaTiO 3 , SrTiO 3 , Bi 4 Ti 3 O 12 , PbTiO 3 ) and a protection layer 132 (which may be Al 2 O 3 , TiO 2 , Ta 2 O 5 , BaTiO 3 , SrTiO 3 , Bi 4 Ti 3 O 12 , PbTiO 3 ). The capacitor may be a ferroelectric capacitor with possible dielectric materials given. Additionally the device ,ay comprise a hydrogen barrier layer 140 formed between the capacitor and a passivating layer 138. The hydrogen barrier layer may be one of Al 2 O 3 , TiO 2 , Ta 2 O 5 , BaTiO 3 , SrTiO 3 , Bi 4 Ti 3 O 12 ,PbTiO 3 . The conductive plug 120 may be provided with a cobalt silicide interface layer or the lower capacitor electrode may be formed from cobalt silicide.