Multi-Die Polylithic Integration Enabled by Heterogeneous Interconnect Stitching Technology (HIST)

In this paper, a multi-die polylithic integration approach using Heterogeneous Interconnect Stitching Technology (HIST) is explored for low-loss, high-density, and low-energy electronic systems. In the HIST approach, stitch-chips, which are either active or passive, are used for such signal pathways between assembled ‘anchor chips,’ while surface-embedded chips utilize 3D face-to-face electrical interconnections. Fine-pitch and multi-height Compressible MicroInterconnects (CMIs) are used to provide low-loss and mechanically robust interfaces between the anchor chips and the stitch-chips as well as the surface-embedded chips. Electrical measurements of the assembled chips are reported and demonstrate robust interconnection. EM simulations show that low-loss signal interconnection (< −0.4 dB) can be achieved by using 90 μm tall CMIs and 500 μm long channels on quartz stitch-chips.