Reference current and reference voltage generation circuit with high power-supply rejection ratio and low power consumption

The invention relates to a reference current and reference voltage generation circuit with a high power-supply rejection ratio and low power consumption. The generation circuit is characterized by comprising PMOS (P-channel Metal Oxide Semiconductor) tube P1, P2 and P3, and NMOS (N-channel Metal Oxide Semiconductor) tube N1, N2, N3, N4 and N5, wherein a power supply VDD (Voltage Drain Drain) is connected with the grid electrode of the N1, the source electrodes of the P1, the P2 and the P3, and the drain electrode of the N1; the source electrode of the N1 is connected with the source electrode of the N3 and the drain electrode of the N4; the grid electrode of the N4 is connected with the grid electrode and the drain electrode of the N5 and the drain electrode of the P2; the grid electrode of the N2 is connected with the grid electrode and the drain electrode of the N3; the source electrodes of the N2, the N4 and the N5 are connected with the power GND; and the drain electrode of the P3 is used as the output end of the reference current generation circuit. The generation circuit provided by the invention is low in power consumption, low in area and high in power-supply rejection ratio.