Two Dimensional Dynamic Multigrained Reconfigurable Hardware

Partial dynamic reconfigurable (PDR) systems designed with state-of-the-art tool chains, like the Early Access Partial Reconfiguration (EAPR) Flow from Xilinx \cite{UG208}, don't exploit the flexibility provided by dynamic an partial reconfiguration features a state of the art FPGA chip offers. For example the utilized chip area and the position for a dynamic area on the chip is traditionally fixed during design-time. Thereby the shape and the size of the area is given by the largest module. If a smaller module is placed on the region of a bigger one, chip area stays unused. These mentioned restrictions are only some examples for the current support of development and run-time tools for reconfigurable hardware architectures. A new approach is shown for exploiting the capability of reconfigurable hardware architectures more efficient than other solutions introduced before. This is achieved through a novel concept of using micro blocks for the communication infrastructure as well as for the functional elements on the FPGA. The granularity of the micro blocks for building up more complex structures on the FPGA is discussed in this paper.