Electroplating with Dielectric Bridges

The electroplating of underlying metal redistribution layers, under-bump metallization (UBM) layers, WLCSP, Cu pillar and other flip chip applications is well established in the semiconductor industry. The use of semi-additive plating can sometimes be adversely affected by the absence of plating occurring in all targeted locations or with plating non-uniformity as a result of front-end fab related structural anomalies. Subsequent analysis has routinely determined that the previously deposited metal seed layer had been discontinuous due to the topography of wafer features. The most predominant types of topographical issues causing discontinuity in the seed layer are related to adverse sidewall profiles of an underlying dielectric layer or an edge of die feature. Typically die streets are kept clear of certain dielectric layers to avoid complications from saw tool wear and residual defects. As such, these particular dielectric layers are usually terminated at or near each die edge on a semiconductor wafer d...