Variability and power management in sub-100nm SOI technology for reliable high performance systems

The ability to fully leverage future CMOS technologies will require a proactive approach to aggressively manage power while characterizing and mitigating the various sources of technology uncertainty. Adaptive techniques that span the full design stack across technology, circuits, and systems/software are required for building future reliable systems. Moreover, the emerging trend of low-power, multi-core-based systems requires very high transistor density and will help drive the transition to unconventional non-planar silicon devices with reduced short channel effects. An integrated design approach between technology development, VLSI design, design automation tools, and micro-architecture is required for optimum system design.