Circuit technologies for a 12 ns 4 Mb TTL BiCMOS DRAM at 3.3 V operation

Circuit technologies are described for a 4-Mb transistor-transistor logic (TTL) BiCMOS DRAM with a 12-ns access time. Successful 3.3-V operation is reported. New circuit technologies, such as a dynamic pull-up input buffer, a common drain BiNMOS decoder, and a direct bootstrap and two-level precharge architecture of the TTL output buffer, make it possible to realize fast access DRAMs. Detailed circuit descriptions of the input buffer and decoder and output buffer are provided, together with a tabular design summary. >