Sub-threshold charge recovery circuits

Embedded systems account for wide range of applications. However, the design of such systems is faced with a diverse spectrum of criteria. The energy consumption, performance, and demanding security concerns are some of the most significant challenges in designing of such systems. With these challenges, the design process can be managed more easily if a flexible logic circuit with the ability of satisfying the above-mentioned concerns is taken into account. To achieve such a logic circuit, in this paper we have combined the sub-threshold operation and charge recovery techniques. Using our technique, lower power consumption, ability of operating at higher frequencies, and more security (to side channel attacks) than the existing logic circuits are achieved. This paper also presents an analytical proof about how sub-threshold charge recovery circuits can meet these characterizations. we have also confirmed our analytical discussions by examining our technique for full adder, and 8 × 8 carry-save multiplier in different frequencies, supply voltages, and CMOS technologies. Detailed SPICE simulations show significant improvements as compared to its existing counterparts in all simulated frequencies and supply voltages.