Hardware Synthesis From Coarse-Grained Specification For Fast HWlSWW osynthesis

paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HWISW cosynthesis. A node in DFG represents a coarse grain block such as FIR and DCT and a pon in a block may consume multiple data samples per invocation; which distinguishes our approach from behavioral synthesis and complicates the problem. In the presented design methodology, a dataflow graph with specified algorithm can he mapped to various hardware structures according to the resource allocation and schedule information. This simplifies the management of the aredperformance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph compared with the previous approaches. Through experiments with some examples, the usefulness of the proposed technique is demonstrated.