Design and Implementation of Boundary-Scan Circuit for FPGA

Based on the characteristics of FPGA, a boundary scan circuit with an extended instruction set in accordance with IEEE 1149.1 standard has been designed and presented in this paper. The circuit can implement the function of built-in self test (BIST) together with FPGA device-programming. In the design, the architecture of the circuit is simplified by deleting redundant instruction registers and sharing some register chains to save the area. Then the design has been integrated into a FPGA prototype chip and implemented by CSMC 0.5 um DPTM standard CMOS process. The experimental results demonstrate that the boundary-scan circuit has realized the desired function of built-in self test and on-chip programming for the FPGA.