P/sup 2/ID in a modern CMOS technology
2002
Plasma process induced damage has been widely investigated in the past few years. We present in this work results from a yearlong study intended to reduce plasma-induced damage in a modern CMOS technology, featuring ultra thin gate oxide. We studied both nMOSFETs and pMOSFETs with a physical gate oxide thickness of 3.5 nm.
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