Parallel testing of random logic LSIs
1984
Circuit functions of logic LSI is becoming more complex year after year as microelectronics-processing technologies progress. This trend is shown well in 16- to 32-bit micro processors and gate array ICs of several thousand gates. with these ICs, numbers of pins have increased and test patterns have become remarkably long. In most cases, therefore, LSI test times become longer. As the result, throughput drops and test quality worsens in LSI testing. To supply LSIs of high reliability and high quality, tester makers need to develop a system of superior measurement precision and high throughput.
We have developed a logic LSI tester based on the true-parallel testing method which holds down the rise of initial cost and greatly enhances throughput (ratio in our company: 1.3 to 1.4 times). This tester is showing excellent operation performance in production lines.
This paper describes how to control the LSI tester based on the true-parallel testing method which is superior in total cost per performance (TCP).
Keywords:
- Correction
- Source
- Cite
- Save
- Machine Reading By IdeaReader
1
References
0
Citations
NaN
KQI