Feasibility study of a novel four transistor silicon-on-insulator static random access memory cell utilizing partial trench isolation

A novel static random access memory (SRAM) cell composed of four thin film silicon-on-insulator (TFSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) intended for 0.5 V operation is proposed. The body regions of the cross-coupled transistor pair are utilized as load resistors. Transfer MOSFETs connecting each SRAM cell to a word line are dynamic threshold MOSFETs (DTMOSs). By utilizing partial trench isolation, the need of special gate shapes for realizing body contacts is eliminated in the proposed SRAM cell. A device simulator with circuit analysis capability reveals that the proposed SRAM cell can be operated properly under a supply voltage of as low as 0.5 V.