A bit-serial column parallel processing architecture for on-sensor discrete Fourier transform

Recent advances in CMOS image sensor technology allow us to realize highly-integrated imaging devices. This paper proposes an architecture of discrete Fourier transform (DFT) for integration on the CMOS image sensor. The proposed bit-serial column parallel DFT scheme is suitable for the integrated image sensor from the viewpoints of high-speed processing, cost-effective implementation, and matching with the column parallel A/D conversion architecture of the CMOS imager. In the case of 256/spl times/256-point DFT, the processing time is estimated to be 2 ms at clock frequency of 100 MHz, which corresponds to the 500 frame/s real-time processing.