Design of Modulo 2n-1 based on Radix-8 Algorithm for RNS & MAC Applications

Abstract- A new architecture, namely, Multiplier-and Accumulator (MAC) based Radix-8 Booth Encoded modulo 2 n -1 Multiplication Algorithm for high-speed arithmetic logics have been proposed and implemented on Xilinx FPGA device. By combining multiplication with accumulation and devising a hybrid type adder the performance was improved. The modified booth encoder will reduce the number of partial products generated by a factor of 2 using radix-4 but by using radix-8 the partial products reduces by a factor of n/3. Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors. The number to be added is the multiplicand, the number of times that it is added is the multiplier, and the result is the product. Each step of addition generates a partial product. Index Terms- Power allocation, resource allocation, orthogonal frequency division multiplexing (OFDM).