Review Article: A technological and electrical study of self-aligned charge-trap split-gate memory devices

Graphical abstractUltra-scaled self-aligned split-gate memories were fabricated with memory gate lengths of 16nm and select gate lengths of 30nm; charge trapping layer is Si3N4. Functionality of such memories was demonstrated, with a programming window of 6.5V (writing) and over than 6V (erasing) at 20µs.Display Omitted Self-aligned split-gate devices fabricated, with memory gate lengths down to 16nm.Functionality of ultra-scaled memories (16nm) demonstrated.Good control of memory gate length and of spacer memory shape.Impact of charge trapping layer, memory gate length and memory gate shape shown. In this work, self-aligned charge trap split-gate devices with memory gate lengths down to 16nm and select gate lengths down to 30nm are fabricated and studied. Main technological issues are addressed. We present the impact of charge-trap layer (SiN or Si-nc), of memory gate length and also of spacer memory shape on electrical results (programming window). We show functionality of ultra-scaled devices, with good programming and erasing performances.