FPGA architecture to search for accelerated pulsars with SKA

This paper presents a design which uses an FPGA (Field Programmable Gate Array) to search for radio pulsars in binary systems for the Square Kilometre Array (SKA). The search pipeline executes Doppler de-acceleration algorithm in real-time to identify binary pulsar spin periods. It involves a very large computation and the algorithm implementation for a real-time execution with power efficiency for the SKA is a challenging task. The design follows a Fourier domain acceleration search method, which is essentially a matched filtering technique, where the complex spectra of the dedispersed time-series are convolved with a set of Doppler demodulation templates. Convolution outputs are systematically summed over a number of harmonics and signatures of periodic signals are detected and passed on for subsequent downstream processing. This design is developed for modern FPGA technology and a prototype of the design is implemented and tested on a commercial FPGA accelerator platform. Salient details of the work are presented in the paper.