DFM Assisted Scan Data Diagnostic Analysis For Fast Systematic Defect Determination

D espite of the inclusion of physical-aware test vectors as part of test patterns in addition to patterns like stuck-at-fault, transition delay and path delay for IC scan test, being able to locate the faults correlated to the failure path remains a challenging and time consuming process. Especially when the failure path might be several hundred micron long, going through close to 10 layers of metal connections and vias and involve few tens of logic ∗jianhao.zhu@globalfoundries.com †thomas.berndt@globalfoundries.com ‡thomas.herrmann@globalfoundries.com §karthiknataraj.krishnamoorthy@globalfoundries.com ¶valerio.perez@globalfoundries.com ‖sky.yeo@globalfoundries.com Colin Chiu Wing Hui et al. DFM Assisted Scan Data Diagnostic Analysis For Fast Systematic Defect Determination Page 26 HCTL Open Science and Technology Letters (HCTL Open STL) Edition on Reconfigurable Computing Embedded, FPGA based, VLSI and ASIC Designs, June 2013 e-ISSN: 2321-6980, ISBN (Print): 978-1-62776-963-1 gates, simply knowing which path is failing can still be like searching a needle in a hay stack in order to find the actual physical fault. The long fault diagnostic cycle could translate into long product yield ramp and could hurt time to market as a result. One method proposed and tested within GLOBALFOUNDRIES to alleviate the long yield debug cycle in narrowing down the root cause is to leverage on the process/design marginality interaction from DFM simulation results. Hotspots markers from DFM simulation are used to correlate/overlay with Design For Test (DFT) failure candidates markers from third party scan diagnosis tools. This paper provides the detail overview of accelerating yield debug through DFM assisted scan data diagnostic correlation. It further showcases a case study of this flow application based on GLOBALFOUNDRIES 28 nm silicon debug data to identify key yield detractors.