Novel differential logic using floating-gate MOS transistors

A new static CMOS differential logic based on multiple-input floating-gate MOS (FGMOS) transistor is proposed. In this circuit configuration, a pair of n-channel multiple-input FGMOS pull down networks is used to replace the nMOS logic tree in the conventional cascode voltage switch logic (CVSL) circuit in order to simplify the circuit structure. By using the advantage that voltage signals are easy to be added by means of floating gate in multiple-input FGMOS transistor, a simple synthesis technique of the n-channel multiple-input FGMOS logic tree by employing summation signal is also discussed. On the basis of the proposed synthesis method, some logic circuits including full adder are designed. HSPICE simulations using TSMC 0.35μm 2-ploy 4-metal CMOS technology with a power supply of 1.5V is utilized to validate the effectiveness of the proposed logic circuits.