Gate Length Reduction Technology for Pseudomorphic In0.52Al0.48As/In0.7Ga0.3As High Electron Mobility Transistors

Gate length reduction technology was developed for pseudomorphic high-electron-mobility transistors (P-HEMTs) applicable to nano-HEMTs. This technology utilizes various reactions between plasmas and dielectrics. Using optimum conditions for reducing gate length through pattern transfer in dielectric etching, we fabricated HEMTs having a sub-30 nm gate length reduced from the initial gate length of 0.13 µm. A HEMT with this technology has merits of both fine length definition beyond the limit of an electron beam (e-beam) lithography system and overcoming the metal filling problem caused by a high aspect ratio. The fabricated devices have high DC and RF performance characteristics, a transconductance of 1.35 S/mm, a maximum saturated current of 800 mA/mm and a cutoff frequency fT of 450 GHz.