Edge Effects in Bottom-Gate Inverted Staggered Thin-Film Transistors

For thin-film transistor (TFT) characterization and simulation, accurate knowledge of the effective channel width ( $W_{\rm EFF}$ ) and effective channel length ( $L_{\rm EFF}$ ) is required, particularly in narrow and/or short devices, where small dimensional variations may result in large overestimation/underestimation of device parameters. Although a substantial amount of research has been done to determine $L_{\rm EFF}$ , there is very little work presented regarding $W_{\rm EFF}$ . Here, we report a design-related existence of current leakage paths along the channel edges in inverted staggered TFT structures. Applied here for the case of amorphous-silicon- and amorphous-oxide-semiconductor-based TFTs, a model is developed to investigate the edge effect from a series of TFTs with various channel widths ( $W$ ). $W_{\rm EFF}$ is found to be larger than the designed $W$ , resulting in an overestimation of the extracted TFT parameters such as the field-effect mobility. It is concluded that a preferred TFT design consists of source and drain electrodes that extend over the active area along the $W$ direction to minimize the edge effects and, hence, improve the accuracy of the extracted TFT parameters.