Pseudo-Differential Time-Domain Integrator Using Charge-Based Time-Domain Circuits

This work proposes a pseudo-differential time-domain integrator using half-delay time-domain registers and adders relying on charge-based time-domain circuits. It is implemented using a 65-nm CMOS Technology and performs first order integration of time-domain information within the range of [4 ns, -4 ns] across temperature -40° C to 80° C. It consumes 740 µW with a supply voltage of 1.2 V at a 100 MHz clock frequency. A delay-locked-loop (DLL) based foreground calibration is used to compensate for process and temperature variations.