A method for producing three-dimensional stacked chip package integrated circuit system and test method

The present invention provides an integrated circuit chip and a method for producing three-dimensional stack system integration testing package, said method comprising: a first lead interconnection pad surface at a boundary surface of the first bare die; second die the second lead interconnection pad surface exposed at a boundary surface; a first dielectric layer is bonded on a second dielectric layer on the second surface of the die and the first die surface; bonded section the first two bare chip semiconductor wafer electroplating, the plating boundary of the second longitudinally fill the cavity from the die, forming the first interconnecting pads and a second lead interconnection leads down a corresponding interconnect pads electrical interconnect plating. The integrated circuit chips are stacked three-dimensional integrated manufacturing system of the present invention is a method and test method of the package, the integrated package system implemented wafer, and electrical interconnection system testing, simple process, high integration, low cost.