A 3.2-to-3.8 GHz Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving –65 dBc In-Band Fractional Spur

A harmonic-mixer-based dual-feedback loop architecture for fractional frequency synthesis is proposed in this letter. By performing frequency subtraction instead of frequency division by using the harmonic mixer in the feedback path, the proposed phase-locked loop (PLL) achieves a unity feedback coefficient, which avoids $\Delta \Sigma $ noise amplification by the loop. This leads to low phase noise and low spurs without the use of complex calibration schemes. The proposed architecture is demonstrated with a 3.2-to-3.8GHz fractional-N PLL prototype in a 65-nm bulk CMOS process that achieves a worst-case in-band fractional spur of −65 dBc.