Strategies for on-chip digital data compression for X-ray pixel detectors

As frame rates of X-ray pixel detectors continue to increase, photon counting will be replaced with charge-integrating pixel array detectors for high dynamic range applications. The continued desire for faster frame rates will also stress the ability of application-specific integrated circuit (ASIC) designers to provide sufficient off-chip bandwidth to reach continuous frame rates of 1 MHz. To move from the current 10 kHz to the 1 MHz frame rate regime, ASIC designers will continue to pack as many power-hungry high-speed transceivers at the periphery of the ASIC as possible. In this paper, however, we present new strategies to make the most efficient use of the off-chip bandwidth by utilizing data compression schemes for X-ray photon-counting and charge-integrating pixel detectors. In particular, we describe a novel in-pixel compression scheme that converts from analog to digital converter units to encoded photon counts near the photon Poisson noise level which achieves a compression ratio of 1.5x independent of the dataset. In addition, we describe a simple yet efficient zero-suppression compression scheme called zeromask (ZM) located at the ASIC edge before streaming data off the ASIC chip. ZM achieves an average compression ratios of >4x, >7x, and >8x for high-energy X-ray diffraction, ptychography, and X-ray photon correlation spectroscopy datasets, respectively. We present the conceptual designs, register-transfer level (RTL) block diagrams, and the physical ASIC implementation of these compression schemes in 65 nm CMOS. When combined, these two digital compression schemes can increase off-chip bandwidth by a factor of 6-12x.