Demonstration of low temperature 3D sequential FDSOI integration down to 50 nm gate length

For the first time, 3D sequential integration is demonstrated down to L G =50nm. Molecular bonding is used to design a perfect a top active layer (thickness control, cristallinity) and a low Thermal Budget (TB) top FET (600°C) has been developed for bottom FET preservation. We demonstrate that this integration is viable for bottom and top MOSFETs with advanced L G . Additionally the low TB process compared to its high temperature counterpart translates in worthy advantages in terms of gate stack: 3A EOT decrease, improved insulating properties. We demonstrate also the smallest Inter-Layer-Dielectric (ILD) thickness down to 23 nm, paving the way to ultra dense and robust SRAMs.