Modeling Differential Through-Silicon-Vias (TSVs) with Voltage Dependent and Nonlinear Capacitance

This paper proposes an equivalent lumped element model for the differential Through Silicon Vias (TSVs) with considering the effect of voltage dependent and nonlinear capacitance. The modeling and analysis of the differential signaling with TSVs play a critical role in designing the high performance TSV channel in the three dimensional integrated circuit (3D IC). TSVs have been mostly modeled assuming that the TSV metal insulator semiconductor (MIS) interface is not biased and the silicon substrate is a lossy, low conductive medium. Ignoring the semiconductor properties of the substrate and the resulting MOS capacitance introduce significant inaccuracies in the TSV modeling. In this paper, we investigate the complementary nature of differential signals which introduces a virtual ground and automatically biases the TSV MIS interface, causing carrier accumulation and depletion. Furthermore, the large digital signal swing makes the depletion region change the depletion width dynamically, which introduces a nonlinear and large signal TSV capacitance. The capacitance is modeled analytically and a new equivalent circuit model for the differential TSVs is proposed accordingly. The impact of the voltage dependent and nonlinear capacitance on the performance of high speed differential signals is analyzed through channel simulations with eye diagram approach.