Making Reliable Memories in an Unreliable World

Reliability is a key concern for VLSI circuits especially so for latches and memories due to their small feature sizes. Particularly, for SRAM cell designs Bias Temperature Instability effects have significant implications on functionality and performance. Here we propose through simulation and modeling an efficient statistical methodology to evaluate and minimize the aging of memory chips. Redundancy has been typically used to resolve failing parts at beginning-of-life. In this approach, we propose to use redundancy to repair critical parts that are most susceptible to aging, thereby optimizing end-oflife yield. Our methodology enables what would have been a very expensive and exhaustive hardware testing approach by identifying optimal repair corners via fast statistical simulations. The methodology takes into consideration reliability effects in the presence of random process variation. This in turn identifies critical repair parts for optimal yield and helps minimize the ever increasing field failure problem.