110 GB/s simultaneous bi-directional transceiver logic synchronized with a system clock

Simultaneous bi-directional transceiver logic (SBTL) doubles data bandwidth because data are transmitted simultaneously in each direction over one wire. The technique has enhanced the cost performance of a commercial high-end UNIX server because the number of LSI signal pins, board signal nets, and connectors have decreased by half. And the SBTL speed can improve to more than 1 Gb/s per pin by using advanced process and circuit technology. The previous high frequency interface uses source-synchronous transmission. But a transmission that is not synchronized with a system clock requires long latency time of several cycles for clock synchronization and data recognition at the receiver LSI. A large interface circuit for the clock synchronization is a disadvantage. Therefore, the SBTL technique synchronized with a system clock has been developed in this work to minimize the latency time even at a high frequency of 1.1 Gb/s per pin. Also, a high-speed signal pin count per LSI is important. Low-noise technique of an output buffer circuit and a package has been developed to get a 100 B high-speed data bus per LSI. The maximum data bandwidth is 110 GB/s per LSI.