Optimized Design of Decoder 2 to 4, 3 to 8 and n to 2n using Reversible Gates

The design of low consumption CMOS circuits, nanotechnologies and quantum computing has becomed more attached to the reversible logic. A set of gates have been recently exploited in reversible computer science for the design of certain circuits. Among them, we find the decoders. In this paper we have exploited a recent study making the design of the decoder 2 to 4, 3 to 8, and n to 2n, our work aims to enhance the previous designs , by replacing some reversible gates by others while maintaining their functionality and improving their performance criteria namely the number of gates (CG), number of garbage outputs (NGO), number of constant inputs(NCI), Quantum cost (QC) and hardware complexity (HC), compared to our study of the base and other recent studies from which we have obtained remarkable results.