Pipeline-design based FPGA implementation of online sequential learning algorithm
2017
A Field Programmable Gate Array (FPGA) implementation of a recently-developed learning algorithm applicable for feedforward neural networks with a single hidden layer is presented in this paper. Of the several possible applications that require online and sequential learning, the one chosen here is that of identification of nonlinear dynamical systems. Real-time implementation of the learning algorithm requires the design of effective computational architectures providing attractive tradeoff between the utilised area and data throughput. In this paper, we propose a pipeline-design based FPGA implementation of the learning algorithm. The methodology is based on the design of custom processing elements and resource sharing between them for different computational stages in a pipelined fashion. The overall design is implemented on a Virtex-6 ML-605 evaluation platform. Such an implementation results in a rather efficient resource utilisation.
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