From the present to the future: Scaling of planar VLSI-CMOS devices towards 3D-FinFETs and beyond 10nm CMOS technologies; manufacturing challenges and future technology concepts

Continues innovation and over-scaling will keep the current SoC's scaling near the historic Moore's Law trend. 3D-TSVs and inductive coupling as well as proper partitioning will allow the opportunity to beat Moore's Law in the next technology nodes.