New Architecture For An AES-EBU Digital Audio Receiver

This paper describes the realization of a digital audio receiver in accordance with the AES3 and S/PDIF format. It illustrates its realization and the performance obtained in terms of output jitter measured on the test chip. This receiver is realized in 3-metal layer 0.5 /spl mu/m CMOS technology, and with a 3.3 V power supply. This low power supply makes the interface compatible with the new generation of VLSI circuits, although it increases the analog design difficulties.