Threshold Switching Enabled Sub-pW-Leakage, Hysteresis-Free Circuits

In this article, we present ultralow leakage logic circuits by combining 3-D memristors with CMOS transistors. Significant leakage current reductions of up to 99% are found by experiments and simulation for a memristive hybrid-inverter if compared with a conventional inverter. Likewise, circuit simulations of memristive hybrid ring oscillators, nand, or full adders show more than 100% gain in energy efficiency per cycle over state-of-the-art circuits. Importantly, the memristive circuits offer hysteresis-free operation. The hysteresis-free operation is due to properly engineered properties--such as the threshold voltage--of the memristors to match the circuit, as well as the self-adaptive filament diameter of our memristor during operation. Lastly, the memristors feature a 10⁸ on-off ratio, enabling both high speed and low leakage (~10 fA) when integrated with a transistor. They also come with a well-controlled filament formation on a ~10-nm footprint, making them ideal to integrate with modern CMOS technology transistors.