Plasma Etching in InAlN/GaN Hemt Technology

The experimental data on the plasma etching of Si3N4 for sub-100 nm gate fabrication for high electron mobility transistors (HEMTs) based on InAlN/GaN heterostructures are analyzed. The influence of the plasma etching process parameters on the plasma-induced damage to the InAlN/GaN heterostructure is considered. The possibility of formation of a 70 nm-length gate InAlN/GaN HEMT using low damage reactive ion etching of Si3N4 is demonstrated.