A New Method for Automatic Generating Simulation Vectors from HDL Descriptions Based-on Path Coverage

A novel method for automatic generating simulation vectors from HDL descriptions based on path coverage and constraint solving is presented. The method only generates constraints for condition expression of the control statements, which can reduce the costs on constraint solving. It can deal with all constraints involving bits, bit-vectors and integers. It can deal with various HDL description styles, and various types of designs. Experimental results on several practical designs show that our method can efficiently improve the simulation vector generation process, which in turn accelerates the design process. The vectors generated by our method can also be used in low-level verification and fault simulation. The prototype system has been applied to verify RTL description of a real 32-bit microprocessor design and complex bugs remained hidden in the RTL descriptions are detected.