High Voltage Device Negative Bias Temperature Instability Improvement with Different Process Conditions

Drastically device dimension shrinkage and rigorous requirement in automotive era puts Negative Bias Temperature Instability (NBTI) at the forefront of reliability issue recently. The PMOS parametric degradation during negative bias high temperature aging can depend on many process variables of the manufacturing flow. A study was carried out to explore the process related dependencies for high voltage PMOS transistor and to increase the device robustness against NBTI stress. In this papers, the process impact on the NBTI degradation were discussed. This investigation work provides methods for significant suppression of the NBTI degradation with silicon rich oxide (SRO) inter layer dielectric (ILD) liner and two-step gate oxidation.