A Design of the Loop Buffering for the Low Power ASIP

In this paper,a multi-segments loop buffering is proposed and it can be used in the design of the ultra low power application specific instruction set processor(ASIP).It is more efficient on the utilization of the loop buffer SRAM compared to the conventional loop buffer techniques.By decreasing the read operations of main program SRAM and the write operations of loop buffer SRAM,the scheme can greatly reduce the power consumption of the program memory.Based on SMIC 0.13μm technology,the new loop buffering is validated in a hearing aid processor.The analysis result shows that the power consumption of the program memory can be reduced by more than 50% with only a little compromise of the area.