The Law that Guides the Development of Photolithography Technology and the Methodology in the Design of Photolithographic Process

Photolithography has been one of the key enabling technologies that continue to support the shrink of semiconductor manufacturing design rules. This technology started from 1 to 1 proximity or contact replication from a mask pattern to wafer image to the current large imaging projection based circuit pattern transfer [1]. The underlying principle for the fast development of the photolithography technology is that the replication process is through light propagation, which can process billions of patterns in parallel. For example, for modern 193 nm immersion process, the minimum pixel size is around 45 nm at a minimum pitch of 90 nm. For a full exposure shot spanning 26 mm by 33 mm, there are a total of 4.2 × 10 11 pixels. If we use ASML NXT1980i exposure tool with a throughput of 275 wafer per hour, it only takes about 13 seconds for one 12 inch wafer exposure or about 160 ms for each exposure shot. In EUV, the parallelism will be higher by more than a factor of 4. This paper will summarize key process window performance parameters, such as imaging contrast/Exposure Latitude (EL), Mask Error Factor (MEF), Depth of Focus (DoF), linewidth uniformity, etc. from typical logic 0.25 µm, 0.18 µm, 0.13 µm, 90 nm, 65 nm, 45 nm, 28 nm, 20 nm, 16/14 nm, 10 nm, 7 nm, and 5 nm technology nodes and key enabling photolithography technologies that have been adopted in time to continually support technology advancement, such as anti-reflection coating, phase shifting mask, chemically amplified photoresist, polarization imaging, optical proximity correction, etc. This summary will result in a law that guides the continuous development of the photolithographic process for generations.