C4NP Lead Free Solder Bumping and 3D Micro Bumping

Semiconductor packaging continues to migrate from wire bond to flip chip first level interconnect to meet aggressive size, weight and electrical performance requirements. In addition, novel System in Package (SiP) approaches utilizing 3D packaging technologies and fine-pitch chip to chip interconnection schemes require advanced lead-free solder bumping technologies. Today, solder electroplating is commonly employed for wafer bumping, especially for fine pitch applications. Wafer level chip scale packaging (WLCSP) typically utilizes solder sphere placement technology to manufacture the bumps. C4NP (Controlled Collapse Chip Connection New Process) has proven to be suitable for a broad range of solder bump pitches, from 3D FC to CSP bump dimensions. As the industry migrates to 300 mm wafer processing and lead-free flip chip intercon nect, C4NP is establishing itself as a viable solder bumping alternative. IBM is ramping production in C4NP and shipping bumped lead-free 300 mm wafers. This paper reviews the C4NP process from mold manufacturing to lead free solder transfer onto 300 mm wafers. Technology applications are summarized, including C4 interconnects and three dimensional (3D) integration. This paper reviews C4NP micro bumping results in support of 3D packaging, and early manufacturing yield results from 300 mm wafer development and manufacturing. Lastly, the most recent lead-free reliability data for both 200mum & 150mum C4 pitch for plated BLMstructures is summarized.