Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial

We investigate on-chip RLC interconnect reduced order modeling problem. A provably realizable and stable model order reduction approach is proposed. To guarantee stability of reduced order circuits, we first employ a realizable reduction for load approximation to preserve the first three driving-point admittance coefficients. Then, we use Hurwitz polynomials to approximate the denominators of original rational transfer functions. We prove that stability can be guaranteed during a hierarchical analysis while circuit response moments can still be matched implicitly. We also give some experimental results to show the accuracy and efficiency of the proposed approach.